In a memory device (e.g. a flash memory), a power supply is required to provide memory cells with voltages and/or electrical currents for normal operations. Generally, there are two power supplies arranged in a conventional flash memory, for example, one of which serves as a core power supply and has a voltage of such as 1.5V or 1.8V; the other serves as an interface power supply and has a voltage of such as from 1.6V to 5.5V.
In such flash memories with two power supplies, when a read operation is required, for example, with a read voltage of 2.5V, the read voltage is preferably provided by the one having a higher voltage among the core power supply and the interface power supply, so as to simplify the circuit design and reduce the power consumption to a largest extent. However, with the development of the integration of integrated circuits, flash memory structures with a single power supply are developed to meet the requirement of simpler configuration of the circuits.
When performing a read operation to a flash memory, the read voltage is usually needed to be adjusted to achieve a better accuracy, for example, in certain flash memories, the read voltage is required to be precisely of 2.5V. FIG. 1 is a schematic block diagram illustrating an existing word-line voltage regulating circuit for single power supply memory. As shown in FIG. 1, a charge pump is used in a flash memory to raise the voltage of the single power supply to a value of for example from 4V to 6V; a controller is provided for monitoring the output voltage PWL of the charge pump, and for refreshing the charge pump by using a refresh signal EPUMPWL when the output voltage of the charge pump is lower than 4V, so as to activate the charge pump to raise the output voltage, and also for prohibiting the refresh operation of the charge pump by using the refresh signal EPUMPWL when the output voltage of the charge pump PWL is higher than 6V.
The output voltage PWL of the charge pump provides electrical power supply to a standby word-line voltage regulator and an active word-line voltage regulator. The refresh signal EPUMPWL outputted by the controller is also used to control the standby word-line voltage regulator such that the standby word-line voltage regulator works to adjust the output voltage PWL of the charge pump to 2.5V when the flash memory is in a standby mode.
Further, when the memory cell is in an active mode, an activate signal SEN is inputted into the active word-line voltage regulator to activate the active word-line voltage regulator, so that the active word-line voltage regulator adjusts the output voltage of the charge pump PWL to 2.5V.
Both the standby word-line voltage regulator and the active word-line voltage regulator use MOS transistor-based voltage regulating circuits to make the output voltage VD25=VDD+Vth, where VDD is the voltage of the single power supply, and Vth is the threshold voltage of a MOS transistor.
However, there are some problems existing in the word-line voltage regulating circuit shown in FIG. 1. First, whenever the memory device is in a standby mode or in an active mode, the voltage PWL in the above-mentioned circuit is always maintained in the range of from 4V to 6V (that is, the average voltage of PWL is about 5V), while the actual output voltage after adjustment is only 2.5V, causing the waste of a half of the voltage PWL, or in other words, a half of the power will be wasted even when there is no electrical current loss.
Second, in the above-mentioned circuit, the output voltage VD25=VDD+Vth, where Vth is the threshold voltage of a MOS transistor and is typically 0.7V, so the voltage of the power supply VDD=1.8V. With the scaling down of integrated circuits, the voltage of the power supply VDD may be scaled down accordingly, but the threshold voltage of the MOS transistor is unable to be proportionally scaled down, as a result, the word-line voltage regulating circuit for single power supply memory shown in FIG. 1 cannot meet the requirement for proportional scale-down of integrated circuits.